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hy5v56b(l/s)f series 4 banks x 4m x 16bits synchronous dram this document is a general product description and is subject to change without notice. hynix does not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.1/oct. 02 2 description preliminary the hy5v56b(l)f is a 268,435, 456bit cmos synchronous dram, ideally suited for the mobile applications which require low power consumption and industrial te mperature range. hy5v56b(l) f is organized as 4banks of 4,194,304x16 hy5v56b(l)f is offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of t he clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read laten cy of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst lengt h of 1,2,4,8, or full page), and the burst count sequence(sequenti al or interleave). a burst of read or write cycles in progress can be termi nated by a burst terminate command or can be interrupted and r eplaced by a new burst read or write command on any cycl e. (this pipelined design is not restricted by a `2n` rule.) features ordering information part no. clock frequency power organization interface package HY5V56BF-h 133mhz normal 4banks x 4mbits x16 lvttl 54ball fbga HY5V56BF-8 125mhz HY5V56BF-p 100mhz HY5V56BF-s 100mhz hy5v56b(l)f-h 133mhz low power hy5v56b(l)f-8 125mhz hy5v56b(l)f-p 100mhz hy5v56b(l)f-s 100mhz ? single 3.30.3v power supply ? all device balls are compatible with lvttl interface ? 54ball fbga (13.5mm x 8.0mm) ? all inputs and outputs refer enced to positive edge of system clock ? data mask function by udqm or ldqm ? internal four banks operation ? auto refresh and self refresh ? 8192 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks
hy5v56b(l/s)f rev. 0.1/oct. 02 3 ball configuration a b c d e f g h j 54 ball fbga 0.8 mm ball pitch vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 clk vss udqm a11 cke a12 a9 a8 a7 a6 vss a5 a4 nc 1 2 3 a b c d e f g h j vddq vddq vssq vssq vdd dq0 vdd vdd dq2 dq1 dq4 dq3 dq6 dq5 dq7 ldqm /cas /ras /we a3 a2 a0 a1 a10 /cs ba0 ba1 7 8 9 9 8 7 3 2 1 < top view > < bottom view >
hy5v56b(l/s)f ball description ball out symbol t ype description f2 clk input clock : the system clock input. all other inputs are registered to the sdram on the rising edge of clk f3 cke input clock enable : controls in ternal clock signal and when deacti- vated, the sdram will be one of the states among power down, suspend or self refresh g9 cs input chip select : enables or dis ables all inputs except clk, cke, udqm and ldqm g7,g8 ba0, ba1 input bank address : select s bank to be activated during ras activ- ity selects bank to be read/written during cas activity h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2, g1 a0 ~ a12 input row address : ra0 ~ ra12, column address : ca0 ~ ca8 auto-precharge flag : a10 f8, f7, f9 ras , cas , we input command inputs : ras , cas and we define the operation refer function truth table for details f1, e8 udqm, ldqm input data mask:controls output buffers in read mode and masks input data in write mode a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 dq0 ~ dq15 i/o data input/output:multip lexed data input/output ball a9, e7, j9, a1, e3, j1 vdd/vss supply power supply for internal circuits a7, b3, c7, d3, a3, b7, c3, d7 vddq/ vssq supply power supply for output buffers e2, g1 nc - no connection
hy5v56b(l/s)f rev. 0.1/oct. 02 5 functional block diagram 4mbit x 4banks x 16 i/o synchronous dram x decoders state machine a0 a1 a11 ba0 ba1 address buffers address registers mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency internal row counter dq0 dq1 dq14 dq15 refresh self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we udqm ldqm 4mx16 bank 3 x decoders x decoders memory cell array y decoders x decoders 4mx16 bank 0 4mx16 bank 1 4mx16 bank 2 x decoders x decoders state machine a0 a1 a12 ba0 ba1 address buffers address registers mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency internal row counter dq0 dq1 dq14 dq15 refresh self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we udqm ldqm 4mx16 bank 3 x decoders x decoders x decoders x decoders memory cell array y decoders x decoders memory cell array y decoders x decoders 4mx16 bank 0 4mx16 bank 1 4mx16 bank 2 x decoders x decoders state machine a0 a1 a11 ba0 ba1 address buffers address registers mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency internal row counter dq0 dq1 dq14 dq15 refresh self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we udqm ldqm 4mx16 bank 3 x decoders x decoders x decoders x decoders memory cell array y decoders x decoders memory cell array y decoders x decoders 4mx16 bank 0 4mx16 bank 1 4mx16 bank 2 x decoders x decoders state machine a0 a1 a12 ba0 ba1 address buffers address registers mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency internal row counter dq0 dq1 dq14 dq15 refresh self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we udqm ldqm 4mx16 bank 3 x decoders x decoders x decoders x decoders memory cell array y decoders x decoders memory cell array y decoders x decoders 4mx16 bank 0 4mx16 bank 1 4mx16 bank 2 memory cell array y decoders x decoders memory cell array y decoders x decoders 4mx16 bank 0 4mx16 bank 1 4mx16 bank 2
hy5v56b(l/s)f rev. 0.1/oct. 02 6 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. dc operating condition (t a = 0 c to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with <=3ns of duration. 3.v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration. ac operating test condition (t a = 0 c to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.output load to measure access times is equivalent to two tt l gates and one capacitor (50pf). for details, refer to ac/dc outp ut load circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any ball relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il -0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement c l 50 pf 1
hy5v56b(l/s)f rev. 0.1/oct. 02 7 capacitance (ta=25 c , f=1mhz) output load circuit dc characteristics i (ta= 0 c to 70 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other balls are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 parameter ball symbol -h -8/p/s unit min max min max input capacitance clk c i1 2.5 3.5 2.5 4.0 pf a0 ~ a12, ba0, ba1, cke, cs , ras , cas , we , udqm, ldqm ci 2 2.5 3.8 2.5 5.0 pf data input / output capaci- tance dq0 ~ dq15 c i/o 4.0 6.5 4.0 6.5 pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4vi ol = +2ma vtt=1.4v rt=250 ? 50pf output 50pf output dc output load circuit ac output load circuit
hy5v56b(l/s)f rev. 0.1/oct. 02 8 dc characteristics ii (ta= 0 c to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2.min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3.HY5V56BF-h/8/p/s 4.hy5v56blf-h/8/p/s 5.hy5v56bsf-h/8/p/s parameter symbol test condition unit note -h -8 -p -s operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 120 120 110 110 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 2 ma i dd2ps cke v il (max), t ck = 1 precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other balls v dd -0.2v or 0.2v 15 ma i dd2ns cke v ih (min), t ck = input signals are stable. 15 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 5 ma i dd3ps cke v il (max), t ck = 5 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other balls v dd -0.2v or 0.2v 30 ma i dd3ns cke v ih (min), t ck = input signals are stable. 20 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 130 130 110 110 ma 1 cl=2 140 140 120 120 auto refresh current i dd5 t rrc t rrc (min), all banks active 220 200 200 200 ma 2 self refresh current i dd6 cke 0.2v normal 3ma3 low power 1.5 ma 4 sl power 900 ua 5
hy5v56b(l/s)f rev. 0.1/oct. 02 9 ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter 2.access times to be measured with input signal s of 1v/ns edge rate, from 0.8v to 2.0v if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter parameter symbol -h -8 -p -s unit note min max min max min max min max system clock cycle time cas latency = 3 tck3 7.5 1000 8 1000 10 1000 10 1000 ns cas latency = 2 tck2 10 10 10 12 ns clock high pulse width tchw 2.5 - 3 - 3 - 3 - ns 1 clock low pulse width tclw 2.5 - 3 - 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 5.4 - 6 - 6 - 6 ns 2 cas latency = 2tac2 -6-6-6-6ns data-out hold time toh 2.5 - 2.5 - 2.5 - 2.5 - ns data-input setup time tds 2 - 2 - 2 - 2 - ns 1 data-input hold time tdh 0.8 - 1 - 1 - 1 - ns 1 address setup time tas 1.5 - 2 - 2 - 2 - ns 1 address hold time tah 0.8 - 1 - 1 - 1 - ns 1 cke setup time tcks 1.5 - 2 - 2 - 2 - ns 1 cke hold time tckh 0.8 - 1 - 1 - 1 - ns 1 command setup time tcs 1.5 - 2 - 2 - 2 - ns 1 command hold time tch 0.8 - 1 - 1 - 1 - ns 1 clk to data output in low-z time tolz 1 - 1 - 1 - 1 - ns clk to data output in high-z time cas latency = 3 tohz3 2.0 5.4 2.0 6 2.0 6 2.0 6 ns cas latency = 2 tohz2 2.0 6 2.0 6 2.0 6 2.0 6 ns
hy5v56b(l/s)f rev. 0.1/oct. 02 10 ac characteristics ii note : 1. a new command can be given trrc after self refresh exit parameter symbol -h -8 -p -s unit note min max min max min max min max ras cycle time operation trc 65 - 68 - 70 - 70 - ns auto refresh trrc 65 - 68 - 70 - 70 - ns ras to cas delay trcd 20 - 20 - 20 - 20 - ns ras active time tras 45 100k 48 100k 50 100k 50 100k ns ras precharge time trp 20 - 20 - 20 - 20 - ns ras to ras bank active delay trrd 15 - 16 - 20 - 20 - ns cas to cas delay tccd 1 - 1 - 1 - 1 - clk write command to data-in delay twtl 0 - 0 - 0 - 0 - clk data-in to precharge command tdpl 2 - 2 - 2 - 2 - clk data-in to active command tdal 5 - 5 - 5 - 5 - clk dqm to data-out hi-z tdqz 2 - 2 - 2 - 2 - clk dqm to data-in mask tdqm 0 - 0 - 0 - 0 - clk mrs to new command tmrd 2 - 2 - 2 - 2 - clk precharge to data output hi-z cas latency = 3 tproz3 3 - 3 - 3 - 3 - clk cas latency = 2 tproz2 2 - 2 - 2 - 2 - clk power down exit time tpde 1 - 1 - 1 - 1 - clk self refresh exit time tsre 1 - 1 - 1 - 1 - clk 1 refresh time tref - 64 - 64 - 64 - 64 ms
hy5v56b(l/s)f rev. 0.1/oct. 02 11 ibis specification i oh characteristics (pull-up) i ol characteristics (pull-down) voltage 100mhz (min) 100mhz (max) 66mhz (min) (v) i(ma) i(ma) i(ma) 3.45 -2.4 3.3 -27.3 3.0 0 -74.1 -0.7 2.6 -21.1 -129.2 -7.5 2.4 -34.1 -153.3 -13.3 2.0 -58.7 -197 -27.5 1.8 -67.3 -226.2 -35.5 1.65 -73 -248 -41.1 1.5 -77.9 -269.7 -47.9 1.4 -80.8 -284.3 -52.4 1.0 -88.6 -344.5 -72.5 0 -93 -502.4 -93 voltage 100mhz (min) 100mhz (max) 66mhz (min) (v) i(ma) i(ma) i(ma) 0000 0.4 27.5 70.2 17.7 0.65 41.8 107.5 26.9 0.85 51.6 133.8 33.3 1.0 58.0 151.2 37.6 1.4 70.7 187.7 46.6 1.5 72.9 194.4 48.0 1.65 75.4 202.5 49.5 1.8 77.0 208.6 50.7 1.95 77.6 212.0 51.5 3.0 80.3 219.6 54.2 3.45 81.4 222.6 54.9 -600 -500 -400 -300 -200 -100 0 00.511.522.533.5 voltage (v) i (ma) i oh min (66mhz) i oh min (100mhz) i oh max (66 /100mhz) 66mhz and 100mhz pull-up 0 50 100 150 200 250 00.511.522.533.5 voltage (v) i (ma) 66mhz and 100mhz pull-down i ol min (100mhz) i ol min (66mhz) i ol max (100mhz)
hy5v56b(l/s)f rev. 0.1/oct. 02 12 device operating option table hy5v56b(l)f-h hy5v56b(l)f-8 hy5v56b(l)f-p hy5v56b(l)f-s cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.0ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 2.0ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 2.0ns cas latency trcd tras trc trp tac toh 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 2.0ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 2.0ns 83mhz(12ns) 2clks 2clks 4clks 6clks 2clks 6ns 2.0ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 2.0ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 2.0ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 2.0ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 2.0ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 2.0ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 2.0ns
hy5v56b(l/s)f rev. 0.1/oct. 02 13 command truth table note : 1. exiting self refresh occurs by asyn chronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank address, ra = row address, ca = column address, opcode = operand code, nop = no operation 3. the burst read sigle write mode is entered by programming the write burst mode bit (a9) in the mode register to a logic 1. command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single- write h x llllx a9 ball high (other balls op code) mrs mode self refresh 1 entry h l lllhx x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
hy5v56b(l/s)f rev. 0.1/oct. 02 14 package information 54 ball 0.8mm pitch 8.0mm x 13.5mm fbga 13.50 6.40 0.80 8.00 0.80 6.40 1.070 0.340 0.450

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